Apple Silicon Rosetta 2 SSE Instruction Support

Hi.

The Rosetta 2 documentation states:
"Rosetta translates all x86_64 instructions, but it doesn’t support the execution of some newer instruction sets and processor features, such as AVX, AVX2, and AVX512 vector instructions".

The documentation does not mention the older SSE instructions (SSE, SSE2, SSE3, SSE4.1 & SSE4.2) so are these supported by Rosetta 2?
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Interestingly, checking cpuid on assembly level indeed indicates SSE2 support in the Rosetta environment.
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arionfromhere
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